FIG. 1 shows a conventional half-bridge driver circuit 100. The circuit 100 is arranged to receive a high-side input HIN and a low-side input LIN, for controlling a high-side output HO and a low-side output LO respectively. The low-side output LO can change between voltage levels COM and VCC. For example, the potential of COM may be at ground (0V) and the potential of VCC may be 20V. The high-side output HO can change between the floating voltage levels VS and VB, where |VB-VS| is the magnitude of the power supply for the high side circuit similar to |VCC-COM| is the magnitude of the power supply voltage for the low side circuit. VS is a floating voltage with reference to COM which can switch between a low voltage below COM and very high voltage above COM (e.g. 600V). The high-side output HO and the low-side output LO are each arranged to drive a respective power switch (not shown) which is further connected to a load. As shown in FIG. 1, the circuit 100 includes an input logic module arranged to receive the high-side input HIN and the low-side input LIN. The input logic module is connected with a low-side circuit providing the low-side output LO and a high-side circuit providing the high-side output HO.
The low-side circuit includes a first path with an under-voltage lockout (UVLO) module connected with VCC, and a second path with a delay module and a buffer module. A low-side driver module formed by two switches is connected across VCC and COM. More particularly, the buffer module is connected with the gate terminals of both switches. The drain terminals of the switches are connected to the low-side output LO.
The high-side circuit includes a pulse generator connected arranged to receive a signal processed by the input logic module. The pulse generator is connected with a level shifting circuit with two switches 101, 102 (e.g., high voltage LDMOS devices) at their gate terminals. Source terminals of the two switches 101, 102 are connected together and to COM. The drain terminal of one switch 101 is connected with a RB node that is connected with a pulse filter 105 and a R terminal of a RS latch 180. The drain terminal of the other switch 102 is connected with a SB node that is connected with the pulse filter 105 and a S terminal of the RS latch 180. The level shifting circuit also includes a resistor 170 arranged between the RB node and VB, and a resistor 172 arranged between the SB node and VB. A buffer module 106 and a high-side driver module with two switches 107, 108 are connected between the output Q of the RS latch 180 and the high-side output HO. The drain terminals of the switches 107, 108 are connected with the high-side output HO.
U.S. Pat. No. 5,514,981 discloses a driver circuit with a similar arrangement to that of FIG. 1.
FIG. 2 shows the waveforms at the high-side input HIN, the SB node, the RB node, and the high-side output HO. As shown in the Figure, during state change of the high-side output HO as the result of the state change of the high-side input HIN, common mode noise exists at both the RB and SB nodes due to capacitance at these nodes. In circuit configurations in which the two resistors 170, 172 are of the same resistance, and the two switching devices 101, 102 (e.g., high voltage laterally diffused metal oxide semiconductor (LDMOS) devices) in the level shifting circuit are of the same size, the common mode noise produced at the RB and SB nodes have substantially the same magnitude. Such common mode noises, if allowed to pass through the pulse filter 105, may potentially undesirably steer the RS latch 180 to the wrong state. In some applications, such latch on/latch off fault can burn or damage the power switches in the external half bridge device driven by the driver circuit. In some applications, even the integrated circuit itself can be burnt or damaged.